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سخنرانی 1. مقدمه و مبانی
مدرس: پروفسور اونور متلو (
تاریخ: 12 ژانویه 2015

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49 پاسخ به “سخنرانی 1. مقدمه و مبانی – کارنگی ملون – معماری رایانه 2015 – اونور متلو”

  6. Memory Hog Problem (Solution, my thoughts): Considering the bottleneck is memory controller and I see the primary reason is the fetch logic is predefined and hard to control as a static parameter. What if we abstract the functions of the memory controller and leave them as API's to be implemented on the system software layer. What I mean is suppose we if we have an interface to implement scheduling logic, we can actually implement the memory access logic on the device driver of the controller and have the device point to this logic. This makes it more generic.

  11. Good video, your seem great, unfortunately the intro is way too long, its almost 30 minutes before I get any relevant information, in the middle, there are too many bits of complicated things combined with irrelevant examples, I had to give up after 27 minutes, because I have no clue when you will actually start talking about the basics of computer architecture, which is the title of the video.

  13. Question isn't their a problem with selecting rows and columns with a Mux, as if you were to activate multiple rows when activating a column you activate all values that have a row activated?

  26. Great explanation, Prof. i'm through 54m into this video, i think using separate row-buffers for each core would solve this issue. Like we do with servers, having multiple cache servers, replica of main servers for data access. Like wise, instead of mutli-cores with one DRAM and single row-buffer, keep the multi-cores with one DRAM but same number of row-buffers as cores. The OS scheduler will do the rest.

  37. Question for anyone to answer: What would you say you need as background knowledge for this class? I am very unlucky to have been thrown into the technology field and to have had very little background in CS. If anyone could please tell me what I should know before going into this class, it would be helpful! Thank you!

  41. Denial of memory service—does one row buffer per each core can serve the purpose?I mean for 2 cores 2 row buffers are need and in DRAM Memory controller we need to set equal priority for both the core requests. @Prof. Onur Mutlu

  42. A key factor in determining the cost of an integrated circuit is volume. Which of
    the following are reasons why a chip made in high volume should cost less?
    1. With high volumes, the manufacturing process can be tuned to a particular
    design, increasing the yield.
    2. It is less work to design a high-volume part than a low-volume part.
    3. Te masks used to make the chip are expensive, so the cost per chip is lower
    for higher volumes.
    4. Engineering development costs are high and largely independent of volume;
    thus, the development cost per die is lower with high-volume parts.
    5. High-volume parts usually have smaller die sizes than low-volume parts and
    therefore have higher yield per wafer

  49. hi Professor . I have question about course , I'm interesting in embedded system so I want understand Computer Architecture for microcontroller and microprocessor arch(ALU – GPR-SP-IR) and the interfacing with memory(how to know ->size of register of memory ,databus , address bus ) to write efficient code .. will this course help me ? if not please tell me link of course which will help me thanks .

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